Parasitic Substrate Coupling in High Voltage Integrated Circuits
By:Pietro Buccella,Camillo Stefanucci,Maher Kayal,Jean-Michel Sallese
Published on 2018-03-14 by Springer

This book introduces a new approach to model and predict substrate parasitic failures in integrated circuits with standard circuit design tools. The injection of majority and minority carriers in the substrate is a recurring problem in smart power ICs containing high voltage, high current switching devices besides sensitive control, protection and signal processing circuits. The injection of parasitic charges leads to the activation of substrate bipolar transistors. This book explores how these events can be evaluated for a wide range of circuit topologies. To this purpose, new generalized devices implemented in Verilog-A are used to model the substrate with standard circuit simulators. This approach was able to predict for the first time the activation of a latch-up in real circuits through post-layout SPICE simulation analysis. Discusses substrate modeling and circuit-level simulation of parasitic bipolar device coupling effects in integrated circuits; Includes circuit back-annotation of the parasitic lateral n-p-n and vertical p-n-p bipolar transistors in the substrate; Uses Spice for simulation and characterization of parasitic bipolar transistors, latch-up of the parasitic p-n-p-n structure, and electrostatic discharge (ESD) protection devices; Offers design guidelines to reduce couplings by adding specific protections.
This Book was ranked at 38 by Google Books for keyword High Voltage.

Book ID of Parasitic Substrate Coupling in High Voltage Integrated Circuits's Books is bGJRDwAAQBAJ, Book which was written byPietro Buccella,Camillo Stefanucci,Maher Kayal,Jean-Michel Sallese
Book which was published by Springer since 2018-03-14 have ISBNs, ISBN 13 Code is 9783319743820 and ISBN 10 Code is 3319743821

Book which have "183 Pages" is Printed at BOOK under CategoryTechnology and Engineering
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